Optimizing the on-chip communication architecture of low power Systems-on-Chip in Deep Sub-Micron technology | BEAMS

Optimizing the on-chip communication architecture of low power Systems-on-Chip in Deep Sub-Micron technology

TitleOptimizing the on-chip communication architecture of low power Systems-on-Chip in Deep Sub-Micron technology
Publication TypePh.D. Thesis
AuthorsLeroy, A.
PublisherUniversité Libre de Bruxelles
Year of Publication2006
Publication Languageeng
Type of Workphd
Citation Keyleroythesis06

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