Microprocessor Architectures | BEAMS

Microprocessor Architectures

Course Information
Course code: 
ELEC-H-473
Study year: 
MA1
Professor: 
Dragomir MILOJEVIC
Assistants: 
Ken HASSELMANN
Assistants: 
Quentin Delhaye

Exam

Two parts: a first one on the theoretical content of the course. You are expected to be able to explain any mecanism presented in the course (SIMD, cache, multithreading, etc.) You can get some inspiration from the open questions asked in the slides.

The second part will be on the laboratories: RiSC16 assembly code, dsPIC33 C code and some assembly code understanding.

For both parts, you cannot have any supporting document with you.

 

 

 

Lectures (now available on http://uv.ulb.ac.be, please go and check if you can access*)

* If all of you can access I will then update only UV  

Labs

Labs take place in the UA5.217 lab (ULB, Solbosh, building U).

Labs are divided into three parts:

  • 4 labs about the RiSC16
  • 2 labs about the dSPic33
  • 3 labs about SIMD instructions in generic x86_64 computers

The goals of these labs are:

  1. Study and use three microprocessor architectures
  2. Learn to deal with a microprocessor documentation

RiSC16 labs assignements:

  • Section 8 of lab 1--2, deadline: one week after lab 2
    • Monday group deadline : 27/02 23:59
    • Wesnesday group deadline : 01/03 23:59
    • Thursday group deadline : 02/03 23:59
  • Section 301 of lab 3, deadline: one week after lab 3
    • Monday group deadline 06/03 23:59
    • Wesnesday group deadline : 15/03 23:59
    • Thursday group deadline : 16/03 23:59

dsPIC33 labs assessment :

  • Some specifications have been released (dsPIC33 exercise) by the assistants, your mission (even if you don't accept it) will be to write some code meeting those specifications. Deadline: 1 week after the second dsPIC33 lab.
  • A new table was provided to ease the computation, check the updated exercise.
  • If you have any question regarding this exercise, send an email to Yannick
  • Reminder: what we evaluate for this exercise is your ability to understand enough your architecture to be able to implement a mathematically correct, efficient and safe computation. Lab 1&2 higlight a lot of specific things you have to use to solve the exercise with flying colors as well as time measurements for basic computations.
  • Monday group deadline 27th March 23:59 /!\ updated
  • C30 compiler for MPLab 8.92: http://ww1.microchip.com/downloads/en/DeviceDoc/mplabc30-v3_31-windows-i... (located at http://www.microchip.com/development-tools/downloads-archive)

SIMD labs assignments:

  • Individual questions during lab 2 and 3 (see SIMD presentation for more details) (continuous assessment) Evaluation is only performed during the labs (no extended deadline)
  • For labs 1 and 2, the assignement is the C and ASM (SIMD) implementation alongside the commented benchmarking of both solutions. As a bonus, you can also compare the performance of the buffer vs streaming file handling and aligned vs unaligned memory.
  • As usual, the deadline is one week after the lab.
  • Send you code only to qudelhay [at] ulb [dot] ac [dot] be
  • For lab 3: send your code and a short report explaining your design for evaluation to qudelhay [at] ulb [dot] ac [dot] be.
  • The SIMD evaluation will be: lab1&2 evaluation+bonus points for lab3.
  • image conversion of raw image to other format using ImageMagick : convert -size 1024x1024 -depth 8 gray:in.raw out.bmp
  • This online tool can also be useful: http://rawpixels.net/
  • To view a file as hexadecimal in vim:
    :%!xxd
    
    And to restore it:
    :%!xxd -r
    
  • Here is a snippet substracting 42 from a vector:
    unsigned char* foo = malloc(sizeof(unsigned char) * 16);
    memset(foo, 42, 16);
    __asm__(
        /* somehow put foo inside xmm3 and your output in xmm2 */
        "psubb %%xmm3, %%xmm2\n"
        /* outputs, inputs, clobbers*/
    );
    
  • The support document has been updated.

Only pdf and .c/.h/.txt/.asm files will be accepted for these assessments. Other file formats will be silently ignored.

There will be a written test at the beginning of the last lab. You already know all the answers to the test.

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