Automated fine-grain partitioning of gate-level netlist for homogeneous/heterogeneous 3D-Stacked Integrated Circuits
In current IC manufacturing process technology roadmaps the pitch of 3D circuit interconnects will soon go well bellow 50um (realistic assumptions target pitches from 10 to 1um and bellow), manual partitioning at higher hierarchical levels of the circuit is becoming insufficient. Due to the size of the problem (hundreds of top-level hierarchical blocks at the top of the hierarchy, and dozens of million of gates at gate-level) automated partitioning methods are mandatory. Contributions of the thesis are twofold. First, the PhD candidate will work on theoretical basis of optimal circuit partitioning. Starting from the existing partitioning algorithms inspired from graph theory, the candidate will propose new algorithms to generate partitions with different optimisation objectives in mind (critical path improvements, interconnect power, etc.). Partitioning will have to operate in hierarchical manner, so that proposed solutions remain viable even when the pitch of the interconnect will be so small to allow partitioning at lower hierarchal levels to ultimately reach gate or even transistor level. Secondly, the algorithms will have to be adapted so that multiple technology targets will be considered at the same time, i.e. the technology target of the given die will have to be automatically chosen with the partition search. Proposed algorithms will be first implemented in a stand-alone application to validate the adopted approach on synthetic benchmark circuits. Finally, real-world complexity circuits will be considered for validation within standard design flow environments for front-, and back-end integration.