Automated gate-level netlists generation for 3D integrated circuits based on user specified partitions
During the design of a 3D integrated circuit, and after system partitioning, we have the information on the position of each gate in the IC stack. However, at final design level we need gate-level netlists on per-die basis. As of today, there is no automated procedure to perform this task that could be extremely difficult to do by hand having in mind the potential number of gates in multi-million gate designs. The goal of this master thesis is to propose an automated framework for such netlist partitioning (information about the partition is user specified). The proposed framework will be validated using various designs and partitioning schemes.
Competences required: C/C++ programming, basics of VHDL modelling and implementation, general knowledge on digital circuits