BARCO/SILEX 3 - Implementation of an FPGA-accelerated HDCP-compliant Tx-Rx Pair
Promotor: Prof. Frederic ROBERT (Frederic [dot] Robert [at] ulb [dot] ac [dot] be)
Barco Silex contactperson: M. Thierry Watteyne, CEO (Thierry [dot] Watteyne [at] barco [dot] com)
This subjet is supposed to be coupled to a 60 working day/10 credits intership (STAG-H501). Internship applications may be directly sent to M. Watteyne: motivation letter + curriculum vitae.
The thesis will be done at Barco-Silex site in Louvain-La-Neuve. Barco-Silex is a specialist in SoC development (ASIC/FPGA), cryptographic engines and video processing. Security platform including HW (in VHDL) and SW has been developed able to be used in different applications (Securing the device, communication, contents…).
The objective is to implement security protocol based on standard like HDCP transmitter/receiver/repeater, EPID or others using existing platform from Barco-Silex. The design (including HW and SW) will be mapped and validated on SoC FPGA (Cortex A9). HW and SW will be developed and validated on existing emulation platform (Zynq or Altera SoC).
The student will have to understand embedded security concept and define an implementation strategy (HW vs SW) with the internal team.
The HW existing platform might have to be adapted. This will be done in VHDL and simulated using main simulation tools suite (i.e. Modelsim).
The SW will be done in C but models or reference can be generated using scripting languages like Tcl or Python. The development platform is SoC-FPGA based.