Gate-level clustering for optimal 3D integration partitioning
Current 3D integration technologies allow implementation of stacked integrated circuits with small 3D structure pitch (appx. 1um). Such low 3D pitch enable system partitioning at a very fine grain, where grain denotes the size of the gate cluster for which we need to decide to which die it will belong (decided during system partitioning). With this master thesis, we want to explore different gate-level clustering techniques to produce block (i.e. graph) view of the placed and routed 2D design. For different designs and clustering techniques different design statistics will be extracted to potentially enable optimal 3D system partitioning.
Competences required: C/C++ programming, basics of VHDL modelling and implementation, general knowledge on digital circuits