[LHC/CMS1] - Developing FPGA data processing solutions at the detector level for the future high luminosity phase of the CMS | BEAMS

[LHC/CMS1] - Developing FPGA data processing solutions at the detector level for the future high luminosity phase of the CMS

Project information
Project type: 
Master thesis
Academic year: 
2017-2018
Status: 
Proposal
Research unit: 
Embedded electronics
BEAMS supervisors
Academic promoter
External supervisors
Prof. Gilles de Lentdecker
Academic co-promoter

Everyone knows the LHC (Large Hadron Collider), the huge particle accelerator that confirmed the existence of the Higgs boson recently.

The « high luminosity » phase of the LHC has the purpose of multiplying by 10 the LHC luminosity (performance) in 2020. The ULB is involved in this project via the IIHE group (High Energy Institute), Prof. Gilles de Lentdecker. The present subject is proposed in collaboration between the IIHE and the BEAMS Embedded Electronics research group since it focuses on FPGA development. 

The goal of the project is to contribute to the development of the data acquisition system (DAQ) that collects the information coming out of the particle detectors, close to the particle collision site. The information coming out of the detectors is collected by a so-called VFAT electronics board and then concentrated, for each group of 24 boards, on a « opto-hybrid » board before being propagated further in the DAQ system. The opto-hybrid board uses an FPGA to collect and process the data.

A new, more powerful generation of the VFAT board (VFAT3) is being released in 2017, in order to be installed in the LHC/CMS next generation electronics. Rewriting the firmware of the FPGA opto-hybrid board is required. The master thesis student will contribute to adapt the FPGA firmware (data processing, automatic calibration of the VFAT3 boards, etc) in order to be ready to install the boards in the LHC in 2018-2020.

 

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