Memory hierarchy exploration of 3D integrated systems
Today memory bottleneck in general purpose computing systems is solved by combining smaller, but high performance SRAM memories organised in deep memory hierarchies (up to L4) with high bandwidth 3D stacked DRAM memories at the end of the memory hierarchy chain (L3 or L4). This model is expected to be adopted soon for high-performance systems and is expected to be adopted in mobile computing soon. In this master thesis, we would like to analyse the applicability of the same approach (3D integration that allows widening of the cache memory hierarchy data-paths) on any general-purpose architecture. The study will focus on analysis of different micro-architectural configurations and real-life applications using well known architecture/memory simulators (e.g. Gem5).
Competences required: C/C++ programming, basics of computer system architecture, general knowledge on digital circuits